1. Field of the Invention
The present invention relates to a technology for testing a semiconductor integrated circuit.
2. Description of the Related Art
Conventionally, detection of a production defect of an integrated circuit is performed by inputting an appropriate signal value to an input pin of the integrated circuit using a tester such as automatic test equipment (ATE), and by comparing the signal value at the output pin with an expected value. The signal value of the input pin and the expected value of the output pin are collectively called a test pattern. When the integrated circuit includes sequential circuit elements (flip flop (F/F), latch and RAM), the complexity of preparing this test pattern increases remarkably. Therefore, scan design called deterministic stored pattern test (DSPT) is widely employed for the integrated circuit.
FIG. 10 is an explanatory diagram of a DSPT. In the DSPT, test patterns TP (input pattern TPin and output pattern TPout) generated by an automatic test pattern generator (ATPG) are stored into a tester (not shown).
A shift register is formed by sequential circuit elements (mainly F/F) in the integrated circuit 1000. This shift register is called a scan path SP. For convenience, four scan paths SP are formed in FIG. 10. A desired input pattern TPin is shifted in from the input pin 1001 at a test, and the value of the shift register is read from the output pin 1002 to the outside after clock impression. Thus, in the DSPT, setting and reading per test pattern TP are repeated to all the sequential circuit elements structuring the scan paths SP in the integrated circuit 1000.
Recently, along with the increased integration of the integrated circuit, the number of sequential circuit elements included in the inside thereof becomes extremely large. Therefore, the application of the DSPT mentioned above comes to be troublesome in the points of increased test time and test data amount. Therefore, a built-in self-test (BIST) comes to be performed.
FIG. 11 is an explanatory diagram of a BIST. In an integrated circuit 1100, a pseudo random number pattern generator 1101 is arranged at the input side of the scan path SP, and a signature analysis device 1102 is arranged at the output side. When a desired control signal is input to an input pin 1111, the pattern generated by the pseudo random number pattern generator 1101 is output to the scan path SP of the integrated circuit 1100, and the output result from the scan path SP is verified by and stored in the signature analysis device 1102. The signature analysis device 1102 compresses and outputs the output result from the scan path SP to the output pin 1112. In other words, it is verified whether this output is identical to the expected value.
To the pseudo random number pattern generator 1101 and the signature analysis device 1102, a linear feedback shift register (LFSR) is frequently used. Since the signature analysis device 1102 compresses and stores the output result as signature, it is called a multiple input signature register (MISR). In the BIST, the pseudo random number pattern generator 1101 is included in the integrated circuit 1100. Accordingly, it is possible to generate quite a large number of test patterns in a short time, and to greatly reduce the test data amount to load to the tester for compressing the test result by the signature analysis device (MISR) 1102.
The MISR is used for compressing the output data in the BIST. Once a value indicating an unknown state (hereinafter, “unknown value”) is taken in, all the registers in the MISR become indefinite, and test cannot be performed. In general, the sequential circuit elements including RAM in the integrated circuit are in unknown state when power is turned on. The process of automatic test pattern generator (ATPG) is simplified by handling the output of the circuit portion that cannot be tested as unknown value. Therefore, it is necessary to handle unknown state. Furthermore, there are cases when it is necessary to cope with unknown values output according to a large amount of unknown states.
As one of countermeasures against an unknown value, there is a mask circuit that masks an unknown value. In general, the mask circuit uses one of three kinds of circuits, a bulk mask, an individual mask, and a random number mask. In the case using any of the mask circuits, there occur different problems according to actions of the respective mask circuits.
FIG. 12 is a circuit diagram of a bulk mask. An unknown value mask device 1202 is a bulk mask circuit. The bulk mask circuit masks all the scan paths SP collectively according to the test data (control signal) input from a tester 1300.
FIG. 13 is a circuit diagram of an individual mask. An unknown value mask device 1202 is an individual mask circuit. The individual mask circuit masks a scan path SP among plural scan paths SP according to test data (control signal) input from the tester 1300. In the case of the individual mask circuit, there is an advantage that it is possible to mask only the unknown value without masking the fault value. However, at every moment when the unknown value at one portion is masked, it is necessary to input test data for one pattern. As a method to perform masking by this method, bist aided scan test (BAST) technology is proposed (for example, Japanese Patent Laid-Open Publication No. 2002-236144).
FIG. 14 is a circuit diagram of a random number mask. The unknown value mask device 1202 is a random number mask circuit. In the random number mask circuit, test data (control signal) output from the tester 1300 is input to the mask signal generating unit 1500. The mask signal generating unit 1500 includes a pseudo random pattern generator and a control circuit. In this mask signal generating unit 1500, the pattern generated by the pseudo random pattern generator is controlled by the control circuit, and the mask signal to each scan path SP is generated. Accordingly, the mask is made to scan path SP with small test data amount by the random number mask.
In the case of the bulk mask, there is an advantage that the mask is made with small test data amount. However, even the value of F/F that is influenced by fault (hereinafter, “fault value”) may be masked when the unknown value is masked. When the fault value is masked, test quality may be deteriorated.
Furthermore, in the case of the individual mask, along with the increase of the circuit scale of the integrated circuit, the number of scan paths SP increases. Accordingly, the data amount per once to specify one scan path increases, and the number of the scan paths SP to be masked increases. And the scan data of the data amount of each time to specify one scan path×the number of unknown values is required. As a result, a large amount of test data for masking the unknown value mask device 1202 is required.
Furthermore, in the case of the random number mask, since the random number to be used for the mask is the pattern that occurs at random, it is not guaranteed to mask all the unknown values. In other words, when the unknown value cannot be masked by the mask signal generated by the mask signal generating unit 1500, it is necessary to change patterns of the mask signal. Therefore, the mask signal must be generated by new random number once again. As a result, it is difficult to generate such a test pattern as to mask all the unknown values, and a high quality test can not be provided.